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1/21 september 2004 m68ar256m 4 mbit (256k x16) 1.8v asynchronous sram features summary supply voltage: 1.65 to 1.95v 256k x 16 bits sram with output enable equal cycle and access time: 55ns, 70ns single byte read/write low standby current low v cc data retention: 1.0v tri-state common i/o automatic power down tfbga48 package ? compliant with lead-free soldering pro- cesses ? standard or lead-free option figure 1. packages fbga tfbga48 (zb) 6x7mm
m68ar256m 2/21 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. tfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 output disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 standby/power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. ac measurement load circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7. address controlled, read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 8. chip enable or output enable controlled, read mode ac waveforms . . . . . . . . . . . . . 12 figure 9. chip enable or ub /lb controlled, standby mode ac waveforms . . . . . . . . . . . . . . . . . 12 table 7. read and standby mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 10.write enable controlled, write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 11.chip enable controlled, write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 12.ub /lb controlled, write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 8. write mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 13.low vcc data retention ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 9. low v cc data retention characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 14.tfbga48 6x7mm - 6x8 active ball array, 0.75mm pitch, bottom view package outline 18 table 10. tfbga48 6x7mm - 6x8 active ball array, 0.75mm pitch, package mechanical data . . . 18 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 11. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9
3/21 m68ar256m revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 12. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
m68ar256m 4/21 summary description the m68ar256m is a 4 mbit (4,194,304 bit) cmos sram, organized as 262,144 words by 16 bits. the device features fully static operation requiring no external clocks or timing strobes, with equal ad- dress access and cycle times. it operates from a single 1.8v ( 150mv) supply voltage. the m68ar256m has an automatic power-down feature, reducing the power consumption by over 99%. the m68ar256m is available in tfbga48 (0.75 mm pitch) package. in addition to the standard ver- sion, the tfbga48 package is also available in lead-free version, in compliance with the st eco- pack 7191395 specification and the rohs (re- striction of hazardous substances) directive. figure 2. logic diagram table 1. signal names ai04890c 18 a0-a17 w dq0-dq15 v cc m68ar256m g 16 e ub lb v ss a0-a17 address inputs dq0-dq15 data input/output e chip enable g output enable w write enable ub upper byte enable input lb lower byte enable input v cc supply voltage v ss ground nc not connected internally du don?t use as internally connected
5/21 m68ar256m figure 3. tfbga connections (top view through package) ai04882b a 6 5 4 3 2 1 e b f a1 a0 g lb a17 dq7 w a12 du a11 a8 nc dq0 a3 a6 a5 a4 e a10 a9 a13 a7 a2 nc c dq4 d dq5 a14 a15 g h dq11 nc ub dq10 dq12 dq13 v ss dq15 dq8 dq9 dq14 dq3 dq2 dq1 v cc v cc v ss dq6 a16 v ss
m68ar256m 6/21 figure 4. block diagram ai04833 row decoder a7 a17 (8) dq0 dq15 (8) column decoder i/o circuits a0 a6 e w g memory array v cc v ss lb lb ub (8) (8) ub lb ub lb
7/21 m68ar256m operation the m68ar256m has four standard operating modes: output disabled, read, write and stand- by/power-down. these modes are determined by the control inputs g , w , e , lb and ub as summa- rized in table 2., operating modes . output disabled. the output enable signal, g , provides high-speed tri-state control of dq0- dq15, allowing fast read/write cycles on the com- mon i/o data bus. the device is in output dis- abled mode when output enable, g , is high. in this mode, lb and ub are don?t care and dq0- dq15 are high impedance. read mode. read operations are used to output the contents of the sram array. the m68ar256m is in the read mode whenever write enable (w ) is high, v ih , with output enable (g ) low, v il , chip enables (e ) is asserted and at least one of the byte enable inputs, ub and lb , is at v il . if only one of the byte enable inputs (ub or lb ), is at v il , the m68ar256m is in byte read mode. if the two byte enable inputs (ub or lb ) are at v il , the m68ar256m is in word read mode. so de- pending on the status of the ub and lb signals, valid data will be available on the lower eight, the upper eight or all sixteen output pins, t avqv after the last stable address providing g is low and e is low. if either of e , g and ub /lb is asserted after t avqv has elapsed, data access will be measured from the limiting parameter (t elqv , t glqv or t blqv ) rath- er than the address.data out may be indetermi- nate at t elqx , t glqx and t blqx , but data lines will always be valid at t avqv . write mode. write operations are used to write data to the sram. the m68ar256m is in the write mode whenever the w and e are low, v il . either the chip enable input (e ) or the write enable input (w ) must be de-asserted during address transitions for subsequent write cycles. when e (w ) is low, and ub or lb is low, write cycle begins on the falling edge of w (e ). when e and w are low, and ub = lb = high, write cycle begins on the first falling edge of ub or lb . therefore, address setup time is referenced to write enable, chip enable or ub /lb as t avwl , t avel and t avbl respectively, and is determined by the latter occurring edge. the write cycle can be terminated by the earlier rising edge of e , w or ub /lb . if the output is enabled (e = low, g = low, lb or ub = low), then w will return the outputs to high impedance within t wlqz of its falling edge. care must be taken to avoid bus contention in this type of operation. data input must be valid for t dvwh before the rising edge of write enable, or for t dveh before the rising edge of e , or for t dvbh before the rising edge of ub /lb whichever occurs first, and remain valid for t whdx , t ehdx and t bhdx respec- tively. standby/power-down mode. the m68ar256m has a chip enable power-down feature which in- vokes an automatic standby mode whenever ei- ther chip enable is de-asserted (e = high) or lb and ub are de-asserted (lb and ub = high). an output enable (g ) signal provides a high speed tri-state control, allowing fast read/write cy- cles to be achieved with the common i/o data bus. operational modes are determined by device con- trol inputs w , e , lb and ub as summarized in the operating modes table (see table 2 ).
m68ar256m 8/21 table 2. operating modes x = v ih or v il . operation e w g lb ub dq0-dq7 dq8-dq15 power standby (deselected) v ih xxxx hi-z hi-z standby (i sb ) xxx v ih v ih hi-z hi-z lower byte read v il v ih v il v il v ih data output hi-z active (i cc ) lower byte write v il v il x v il v ih data input hi-z active (i cc ) output disabled v il v ih v ih x x hi-z hi-z active (i cc ) upper byte read v il v ih v il v ih v il hi-z data output active (i cc ) upper byte write v il v il x v ih v il hi-z data input active (i cc ) word read v il v ih v il v il v il data output data output active (i cc ) word write v il v il x v il v il data input data input active (i cc ) output disabled v il x v ih x x hi-z hi-z active (i cc )
9/21 m68ar256m maximum rating stressing the device above the rating listed in the absolute maximum ratings" table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 3. absolute maximum ratings note: 1. one output at a time, not to exceed 1 second duration. 2. compliant with the st 7191395 specification for lead-free soldering processes. 3. not exceeding 250c for more than 30s, and peaking at 260c. 4.up to a maximum operating v cc of 1.95v only. symbol parameter value unit i o (1) output current 20 ma t a ambient operating temperature ?55 to 125 c t stg storage temperature ?65 to 150 c t lead lead temperature during soldering (2) 260 (3) v cc supply voltage ?0.5 to 2.5 v v io (4) input or output voltage ?0.5 to v cc + 0.5 v p d power dissipation 1 w
m68ar256m 10/21 dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 4. operating and ac measurement conditions figure 5. ac measurement i/o waveform figure 6. ac measurement load circuit parameter m68ar256m v cc supply voltage 1.65 to 1.95v ambient operating temperature range 1 0 to 70c range 6 ?40 to 85c load capacitance (c l ) 30pf output circuit protection resistance (r 1 ) 15.3k ? load resistance (r 2 ) 11.3k ? input rise and fall times 1ns/v input pulse voltages 0 to v cc input and output timing ref. voltages v cc /2 output transition timing ref. voltages v rl = 0.3v cc ; v rh = 0.7v cc ai04831 v cc i/o timing reference voltage 0v v cc /2 v cc output timing reference voltage 0v 0.7v cc 0.3v cc ai03853 v cc out c l includes probe and 1ttl capacitance device under test c l r 1 r 2
11/21 m68ar256m table 5. capacitance note: 1. sampled only, not 100% tested. 2.at t a = 25c, f = 1 mhz, v cc = 1.8v. table 6. dc characteristics note: 1. average ac current, cycling at t avav minimum. 2. e = v il , lb or/and ub = v il , v in = v il or v ih . 3.e 0.2v, lb or/and ub 0.2v, v in 0.2v or v in v cc ?0.2v. 4. output disabled. figure 7. address controlled, read mode ac waveforms note: e = low, g = low, w = high, ub = low and/or lb = low. symbol parameter (1,2) test condition min max unit c in input capacitance on all pins (except dq) v in = 0v 6pf c out output capacitance v out = 0v 8pf symbol parameter test condition m68ar256m -l -n min max min max unit i cc1 (1,2) operating supply current v cc = 1.95v, f = 1/t avav , i out = 0ma 55ns 10 ma 70ns 6 6 ma i cc2 (3) operating supply current v cc = 1.95v, f = 1mhz, i out = 0ma 22ma i li input leakage current 0v v in v cc ?11?11a i lo (4) output leakage current 0v v out v cc (3) ?11?11a i sb standby supply current cmos v cc = 1.95v, e v cc ?0.2v or lb =ub v cc ?0.2v, f = 0 15 15 a v ih input high voltage 1.4 v cc + 0.4 1.4 v cc + 0.4 v v il input low voltage ?0.5 0.4 ?0.5 0.4 v v oh output high voltage i oh = ?100a 1.5 1.5 v v ol output low voltage i ol = 100a 0.2 0.2 v ai03956b tavav tavqv taxqx a0-a17 dq0-dq7 and/or dq8-dq15 valid data valid
m68ar256m 12/21 figure 8. chip enable or output enable controlled, read mode ac waveforms note: write enable (w ) = high. figure 9. chip enable or ub /lb controlled, standby mode ac waveforms ai03957 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz valid a0-a17 e g dq0-dq15 valid tblqv tblqx tbhqz ub, lb ai03856 tpd i cc tpu i sb 50% e, ub, lb
13/21 m68ar256m table 7. read and standby mode ac characteristics note: 1. test conditions assume transition timing reference level = 0.3v cc or 0.7v cc . 2. at any given temperature and voltage condition, t ghqz is less than t glqx , t bhqz is less than t blqx and t ehqz is less than t elqx for any given device. 3. these parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to o utput voltage levels. 4.tested initially and after any design or process changes that may affect these parameters. symbol parameter m68ar256m unit 55 70 t avav read cycle time min 55 70 ns t avqv address valid to output valid max 55 70 ns t axqx (1) data hold from address change min 5 5 ns t bhqz (2,3) upper/lower byte enable high to output hi-z max 20 25 ns t blqv upper/lower byte enable low to output valid max 55 70 ns t blqx (1) upper/lower byte enable low to output transition min 5 5 ns t ehqz (2,3) chip enable high to output hi-z max 20 25 ns t elqv chip enable low to output valid max 55 70 ns t elqx (1) chip enable low to output transition min 5 5 ns t ghqz (2,3) output enable high to output hi-z max 20 25 ns t glqv output enable low to output valid max 25 35 ns t glqx (2) output enable low to output transition min 5 5 ns t pd (4) chip enable or ub /lb high to power down max 55 70 ns t pu (4) chip enable or ub /lb low to power up min 0 0 ns
m68ar256m 14/21 figure 10. write enable controlled, write ac waveforms figure 11. chip enable controlled, write ac waveforms ai03958b tavav twhax tdvwh data input a0-a17 e w dq0-dq15 valid tavwh twlwh tavwl twlqz twhdx twhqx tblwh ub, lb telwh ai03959b tavav tehax tdveh a0-a17 e w dq0-dq15 valid taveh tavel teleh tehdx data input tbleh ub, lb twleh
15/21 m68ar256m figure 12. ub /lb controlled, write ac waveforms note: 1. during this period dq0-dq15 are in output state and input signals should not be applied. ai03987b tavav tbhax tdvbh data input a0-a17 e w dq0-dq15 valid tavbh tbhdx tblbh ub, lb data (1) tavbl telbh twlbh
m68ar256m 16/21 table 8. write mode ac characteristics note: 1. at any given temperature and voltage condition, t wlqz is less than t whqx for any given device. 2. these parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to o utput voltage levels. symbol parameter m68ar256m unit -l -n 55 70 55 70 t avav write cycle time min55705570ns t avbh address valid to lb , ub high min45604560ns t avbl addess valid to lb , ub low min0000ns t aveh address valid to chip enable high min 45 60 45 60 ns t avel address valid to chip enable low min 0 0 0 0 ns t avwh address valid to write enable high min 45 60 45 60 ns t avwl address valid to write enable low min 0 0 0 0 ns t bhax lb , ub high to address transition min 0 0 0 0 ns t bhdx lb , ub high to input transition min 0 0 0 0 ns t blbh lb , ub low to lb , ub high min 45 60 45 60 ns t bleh lb , ub low to chip enable high min 45 60 45 60 ns t blwh lb , ub low to write enable high min 45 60 45 60 ns t dvbh input valid to lb , ub high min25302530ns t dveh input valid to chip enable high min 25 30 25 30 ns t dvwh input valid to write enable high min 25 30 25 30 ns t ehax chip enable high to address transition min 0 0 0 0 ns t ehdx chip enable high to input transition min 0 0 0 0 ns t elbh chip enable low to lb , ub high min 45 60 45 60 ns t eleh chip enable low to chip enable high min 45 60 45 60 ns t elwh chip enable low to write enable high min 45 60 45 60 ns t whax write enable high to address transition min 0 0 0 0 ns t whdx write enable high to input transition min 0 0 0 0 ns t whqx (1) write enable high to output transition min 5 5 5 5 ns t wlbh write enable low to lb , ub high min45604560ns t wleh write enable low to chip enable high min 45 60 45 60 ns t wlqz (1,2) write enable low to output hi-z max 20 20 20 20 ns t wlwh write enable low to write enable high min 45 60 40 50 ns
17/21 m68ar256m figure 13. low v cc data retention ac waveforms table 9. low v cc data retention characteristics note: 1. all other inputs at v ih v cc ?0.2v or v il 0.2v. 2. tested initially and after any design or process changes that may affect these parameters. t avav is read cycle time. 3. no input may exceed v cc +0.2v. symbol parameter test condition min typ max unit i ccdr (1) supply current (data retention) v cc = 1.0v, e v cc ?0.2v or ub = lb v cc ?0.2v, f = 0 (3) 0.5 3 a t cdr (1,2) chip deselected to data retention time 0ns t r (2) operation recovery time t avav ns v dr (1) supply voltage (data retention) e v cc ?0.2v or ub = lb v cc ?0.2v, f = 0 1.0 v ai03859 data retention mode tr 1.95v tcdr v cc 1.65v v dr > 1.0v e or ub/lb e v dr ? 0.2v or ub = lb v dr ? 0.2v
m68ar256m 18/21 package mechanical figure 14. tfbga48 6x7mm - 6x8 active ball array, 0.75mm pitch, bottom view package outline note: drawing is not to scale. table 10. tfbga48 6x7mm - 6x8 active ball array, 0.75mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.250 0.400 0.0098 0.0157 a2 0.790 0.0311 b 0.400 0.350 0.450 0.0157 0.0138 0.0177 d 6.000 5.900 6.100 0.2362 0.2323 0.2402 d1 3.750 0.1476 ddd 0.100 0.0039 e 7.000 6.900 7.100 0.2756 0.2717 0.2795 e1 5.250 0.2067 e 0.750 ? ? 0.0295 ? ? fd 1.125 0.0443 fe 0.875 0.0344 sd 0.375 ? ? 0.0148 ? ? se 0.375 ? ? 0.0148 ? ? e1 e d1 d eb a2 a1 a bga-z43 ddd fd fe sd se e ball "a1"
19/21 m68ar256m part numbering table 11. ordering information scheme for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest to you. example: m68ar256 m l 55 zb 6 t device type m68 mode a = asynchronous operating voltage r = 1.65 to 1.95v array organization 256 = 4 mbit (256k x16) option 1 m = 1 chip enable; write and standby from ub and lb option 2 l = l-die n= n-die speed class 55 = 55 ns 70 = 70 ns package zb = tfbga48 6x7mm, 0.75mm pitch operative temperature 1 = 0 to 70 c 6 = ?40 to 85 c shipping blank = standard packing (tray) t = tape and reel packing e = lead-free package, standard packing (tray) f = lead-free package, tape and reel packing
m68ar256m 20/21 revision history table 12. document revision history date version revision details july 2001 -01 first issue 23-oct-2001 -02 speed class changed from 80 to 70ns 20-may-2002 -03 document globally revised 01-oct-2002 3.1 revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 03 equals 3.0) part number changed 09-oct-2002 3.2 part number clarified 20-feb-2004 4.0 n-die added. tfbga48 7 x 8mm replaced by tfbga48 6 x 7mm i cc1 and i sb updated in table 6.dc characteristics . n-die ac write characteristics added in table 8. write mode ac characteristics . minor content modifications. lead-free package option added in table 11.ordering information scheme . 03-aug-2004 5.0 connection e3 updated in figure 3., tfbga connections (top view through package) . 27-sep-2004 6.0 t pd and t pu modified in table 7., read and standby mode ac characteristics . document structure updated without modifications of the content.
21/21 m68ar256m information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replac es all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. ecopack is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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